Energy Efficient Embedded Non-Volatile Memory & Logic Based on Ferroelectric Hf(Zr)O2

In this newsletter, we report advances on interface engineering, capacitor integration and FeFET logic design in the frame of the H2020 3eFERRO project.

3eFERRO project introduces new ferroelectric material Hf(Zr)O2 to make FeRAM competitive NVM candidate for IoT. The project regroups 8 partners from 5 UE countries, including:

– CEA,

– ST Microelectronic,

– Namlab (the leader in the field of ferroelectric HfO2),

– 5 large technology laboratories.

The newsletter 5 highlights advances on the three following part of the project:

  1. Interface engineering
  2. Capacitor integration
  3. FeRAM and FeFET based logic desgin.

The newsletter 4 highlights advances on the three following part of the project:

  1. Exploration of the Design Space of ferroelectric-based circuits through a Design-Technology co-optimization approach
  2. Imprint in TiN/HfZrO2/Ge capacitor structures
  3. High k workshop virtual seminars programme

The newsletter 3 highlights advances on the three following part of the project:

  1. Interface engineering HfO2/TiN published in Applied Physics Letters
  2. Successful co-integration of HZO scaled capacitors above 130 nm CMOS with excellent ferroelectric performances
  3. Novel FeFET-based fine-grain Logic in Memory cells.

References et collaborations:

https://www.3eferro.eu/

https://publishing.aip.org/publications/journals/special-topics/apl/ferroelectricity-in-hafnium-oxidematerials-and-devices/

Contact:

Bertrand Vilquin

mail :

INL CNRS
Advances in 3eFERRO project on: (a) capacitor integration and the resulting switching efficiency, (b) interface engineering HfO2/TiN, and (c) improvement in transistors count for novel FeFET based LUT design
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