Photonic systems

Our focus consists of developing novel devices and systems, in particular exploiting CMOS-compatible platforms and the integration of electronics and photonics for applications in security and computing. Specifically, our approach lies at the frontier between the device and the system where a strong expertise in their co-integration is required for achieving optimal performance.

The main research areas are i) hardware integrity and information security, ii) stochastic and neuromorphic computing and iii) high-bandwidth energy-efficient communications.

Hardware integrity and information security

The huge number of interconnected devices within the IoT world (42 billion expected in 2025) demands for enhanced security both at the identification level (hardware integrity) as well as at the authentication level (information security). Current hardware approaches avoiding the digital storage of a secret key for building security layers do not satisfy contemporarily the requirements of scalability, robustness and reliability within the security landscape.
In this context we focus on the development of photonic-based physical unclonable functions (PUFs) which are expected to provide a higher degree of robustness compared to pure electronic approaches thanks to the larger number of physical quantities associated with a light beam as well as scalability and reliability through the leveraging of CMOS-compatible platforms and machine learning techniques.

Collaborations: INL (Heterogenous System Design Group) and RMIT (Microplatforms Research Group)
On-going projects: Advanced PHotonic-ELectronic Identification and Authentication (APHELIA) – IDEXLYON IMPULSION grant

Stochastic and neuromorphic computing

The current computing limitations (e.g. energy efficiency) of binary Von-Neumann architectures demands to explore less traditional computing paradigms. Particularly, approaches exploiting non-volatile memory (NVM) elements and architectures e.g. mimicking the brain functioning (neuromorphic computing) propose orders of magnitude better performance in terms of energy efficiency compared to traditional architectures.
In this context we focus on the development of electronic-photonic systems exploiting phase change materials (PCMs) which have a threshold-dependent activation and memory-dependent response that can mimic the behavior of a neuron or a synapse or that can function analogously to a multiply and accumulate (MAC) logic block for stochastic computing.

Collaborations: INL (Heterogenous System Design Group and Metasurfaces and Tunable Materials Division), CEA-LETI (Materials and Optical divisions), Concordia University (ECE Dept.), University of Bourgogne (Photonics Dept.), Polytechnic of Turin (TEST and SYSBIO Groups), RMIT (Microplatforms Research Group).

High-bandwidth energy-efficient communications

The current demand for higher computing performance in terms of bandwidth and energy efficiency cannot be met anymore by purely electronic architectures because of intrinsic limitations in electrical interconnects and transistor-scaling (Moore’s law) vs performance.
More than Moore paradigms such as the integration of electronic and photonic systems have been demonstrated as a potential solution to solve the communication bottleneck in computing.
In this context we focus on the development of novel devices (e.g. grating couplers, modulators…), systems and architectures based on CMOS-compatible platforms at telecom wavelengths starting from first principles and rigorous device- and system-level simulations.

Collaborations: INL (Heterogenous System Design Group), Boston University (Popović Research Group), University of Berkeley (Stojanović Research Group), MIT (Physical Optics and Electronics Group), College of Nanoscale and Science Engineering (CNSE)

Group members

  • Coordinator: Fabio Pavanello
  • Permanent : Xavier Letartre, Sébastien Cueff, Ian O’Connor (CSH team), Alberto Bosio (CSH), Sébastien Le Beux (CSH), Cédric Marchand (CSH)
INL CNRS
Monolithic electronics-photonics integration in a modified 65 nm bulk CMOS node. (Adapted from Atabaki, Moazeni, Pavanello et al., Nature 556, 316-318 (2018)).
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