3D monolithically integrated SPAD pixels in advanced CMOS FDSOI technology


N° ANR-18-CE24-0010 / Period: Nov 2018 – April 2022

Project leader: Pr. Francis Calmon (francis.calmon@insa-lyon.fr)


- INL (Institut des Nanotechnology de Lyon) inl
Pr. Francis Calmon (francis.calmon@insa-lyon.fr)

- ICUBE (Laboratoire des sciences de l'ingénieur, de l'informatique et de l'imagerie) icube
Pr. Wilfried Uhring (wilfried.uhring@unistra.fr)

-CEA-LETI leti
Dr. Gabriel Parès (gabriel.pares@cea.fr)

With support of :



Single-Photon Avalanche Diodes (SPAD) have been widely studied and successfully implemented for the detection of weak optical signals in the visible and near-infrared spectrum range (NIR). They are able of capturing individual photons with typically sub-nanosecond timing resolution, which make them suitable for a wide area of application such as low light detection, time of flight measurements (e.g. telemeter) and more recently in quantum random number generators. The use of CMOS technologies allows low-cost, compact and reliable implementation of SPADs. Thus, CMOS SPAD-based sensors enter rapidly the consumer market. However, for more demanding applications such as image sensors (for 3D and/or time-resolved imaging), several technological challenges still need to be tackled. The current research efforts are mainly focusing on the increase of the fill factor and the photon detection efficiency for NIR photons. One way to keep the CMOS compatibility is to implement SPAD-based sensors with 3D-stacking of two tiers; one hosting the SPADs (with backside illumination), the other one hosting the associated electronics. Such a 3D-integration remains delicate and quite expensive since two dies need to be designed and fabricated, and then 3D assembled (at wafer level).

SPAD-FDSOI concept (key idea)

SPAD-FDSOI research program aims at developing high performances - high fill-factor SPAD pixel integrated in advanced standard CMOS technology. The key idea is to use some specific features of advanced CMOS 28nm FDSOI (Fully Depleted Silicon-on-Insulator) technology to develop a novel 3D monolithically integration of SPAD pixel with back-side illumination. The expected benefits of such an integration are much higher fill factor (>50%), with state of-the-art performances (Dark Count Rate - DCR, Photon Detection Probability - PDP, spatial and time resolutions), low power resulting from the FDSOI technology choice and a cost effective and reliable solution for 3D SPAD and associated electronics implementation due to the monolithically integration (no need of staking two tiers). In this novel approach for SPAD integration, the avalanche diode is implemented beneath the buried oxide using the existing doped layers (used for transistor back-biasing) while the associated electronics (quenching and addressing) is implemented in the ultra-thin top silicon layer, see Figure 1 (this concept has been proposed by the present coordinator in 2017, preliminary simulation study has been published [1], first very encouraging experimental results has been submitted for publication at ESSDERC 2018 conference [2]).

Figure 1: Cross section of the proposed 3D monolithically integration of SPAD and associated electronics in advanced CMOS FDSOI technology (scales are not respected).

[1] M. M. Vignetti, F. Calmon, P. Lesieur, A. Savoy-Navarro “Simulation study on a novel 3D SPAD pixel in FDSOI technology” Elsevier Solid State Electronics, Vol. 128, pp. 163–171, February 2017, doi: 10.1016/j.sse.2016.10.014 (DOI: 10.1016/j.sse.2016.10.014).
[2] T. Chaves de Albuquerque, F. Calmon, R. Clerc, P. Pittet, Y. Benhammou, D. Golanski, S. Jouan, D. Rideau, A. Cathelin “Integration of SPAD in 28nm FDSOI CMOS technology” ESSDERC 2018, 3-6 sept. 2018, Dresden, Germany (DOI: 10.1109/ESSDERC.2018.8486852).