3D monolithically integrated SPAD pixels in advanced CMOS FDSOI technology

SPAD FD-SOI

Main objectives

The objective of our project is to investigate an original CMOS SPAD architecture implemented in FDSOI (Fully Depleted Silicon-on-Insulator) technology allowing much higher fill-factor with state of the art SPAD performances, embedded high performance and low power electronics, and without the need of expensive 3D staking process at wafer level.

The main goal is to provide the proof of concept including the design, optimization and characterization of 3D monolithically integrated SPAD array and associated electronics in commercial CMOS 28nm FDSOI technology.
The main challenging issues are the:

  • Achievement of state-of-the-art SPAD pixel characteristics in terms of after pulsing, Dark Count Rate, Photon Detection Probability‚Ķ.
  • Optimization of the SPAD array architecture to preserve a safe and quasi-normal operation of the associated electronics implemented in the top thin silicon layer when avalanches occur (low risk using a configuration where the cathode is used as the SPAD sensing node, the p-well could remain grounded, shielding the electronics implemented above the Buried Oxide).
  • Die post-processing for Back Side Illumination (BSI), i.e. substrate thinning and passivation. BSI is now usual for CMOS imagers; thinning, usually realized at the wafer level, is more challenging at the die level. In this project, specific thinning process at the die level will be developed as wafer level processing costs are prohibitive for prototyping.

Tanks to the original architecture, numerous opportunities appear, such as:

  • The development of original isolated quenching detection electronics thanks to the back biasing effect (configuration where the SPAD cathode is at constant voltage and the anode is the moving node allowing to detect the SPAD event with a sensing circuitry).
  • The introduction of “light trapping” concept to increase PDP in NIR range thanks to BSI and additional nanostructured layer after die thinning.

Finally, a parametrized SPAD cell may be available for the designers using CMOS 28nm FDSOI technology allowing to develop fully integrated SPAD-based circuits.