Context and Objectives

Recently, major security issues associated with the advancement of reverse engineering and cyber-attack techniques have emerged on a global scale, affecting hardware integrity and information security. In particular, counterfeit chips have been found in several defense and security systems, potentially capable of undermining system security and acquiring sensitive information or protected data. Physical unclonable functions (PUFs) are hardware solutions to combat counterfeiting at the circuit level and to generate cryptographic keys. They rely on the unpredictability of complex responses, highly dependent on manufacturing tolerances, and avoid local storage of keys in memory and thus the possibility that information is acquired by simple memory access through malware. The most frequently used solutions are implemented in electronics using the manufacturing tolerances of transistors whose character is random and not clonable.

Electronic approaches have several advantages such as their native implementation in CMOS technology and their flexibility to integrate with other systems. However, a certain degree of weakness against machine learning attacks has been demonstrated recently for these approaches because of their limited complexity in terms of degrees of freedom and their need for complex error correction units that consume a lot of power and surface area due to the classical limitations of transistors such as their ageing and temperature dependence. Concerning the other approaches studied to realize PUFs, several demonstrations using optics have been proposed, presenting very interesting performances in terms of randomness and richness of responses. Nonetheless, these approaches are often based on bulky optics with a low level of integration, which makes them expensive.

The PHASEPUF project aims at developing a new class of photonic PUFs, exploiting CMOS compatible platforms, and at demonstrating their advantages in terms of power consumption and compactness, as well as robustness and reliability, thanks to a greater richness of physical phenomena compared to electronic solutions based on the transfer of binary signals and subject to machine learning attacks. Several architectures and methods of operation will be investigated during the project, favoring solutions with a high level of integration and which are compatible with low-cost mass production. These solutions will be evaluated with respect to electrical and machine learning attacks and their robustness and reliability will be studied by fault injection to emulate their ageing and behavior against temperature fluctuations.


To achieve the objectives mentioned above the work will be divided in 2 phases:


Different architectures for strong and weak PUFs will be evaluated by means of device and system-level simulations. The most relevant architectures will be then fabricated in Silicon Photonics technology based on CMOS-compatible platforms. These platforms will allow access to a series of photonic building blocks already developed and optimized that will be leveraged in PUF design.


The prototypes will be characterized by using an electro-optic test setup in order to assess their performance. Different types of characterization will be performed based on on-chip measurements as well as FPGA-based testing boards. Temperature-controlled experimennts will allow to assess their degree of stability against temperature fluctuations and fault injection attacks will be used to assess their robustness.

Data analysis

The collected CRPs will be analysed to assess their suitability as PUFs. Specifically, machine learning attacks/modelling will be carried out on strong PUFs as well as statistical tests on weak PUFs. Error-correction codes will be investigated to enhance their degree of strength as well as other approaches based on bit strings manipulation e.g., XOR operation between sub-sequences etc.