Integration of SPAD in CMOS 28nm FDSOI technology
We propose an original Single Photon Avalanche Diode (SPAD) architecture, directly implemented in advanced CMOS FDSOI – Fully Depleted Silicon-on-Insulator technology (also referred as “Ultra-Thin Body and Buried Oxide – UTBB SOI technology”), allowing optimization of the fill-factor, without the need of expensive 3D staking process [1]. The SPAD is implemented below the buried oxide (BOX) while the transistors for CMOS electronics are placed in the thin silicon layer (see Fig. 1). This SPAD architecture is then intrinsically 3D as the logic circuitry (quenching, addressing, processing) is placed above the SPAD (with back side illumination after die thinning, for near infrared light capture).
To our knowledge, it is the first demonstration of SPAD devices in a FDSOI technology. This work has been carried out in the CMOS28FDSOI technology from STMicroelectronics, with no process changes and no design rule violations.
In [2], we present the characterization study in dark conditions of the first SPAD test-chip fabricated in an advanced FDSOI CMOS technology. The diode is designed using the P-well and deep N-well layers conventionally used for transistor back-biasing (see Fig. 2). A first test-chip has been fabricated including various SPAD cells (squared and octagonal shapes, different guard ring widths) and characterized in dark conditions. Electroluminescence cartography has been analyzed, indicating the advantage of an octagonal shape to avoid premature edge breakdown (see Fig. 1). A quite low SPAD breakdown voltage (~10V) is obtained at room temperature due to the native abrupt junction doping profiles. Consequently, a low activation energy, that is the signature of the band-to-band and field-enhanced trap assisted tunneling, has been extracted from dark count rates (DCR). DCR is of few tens of Hz/µm² at room temperature for 0.3 V excess bias.
The study will be pursued for more statistical data acquisition and for SPAD characterization under illumination. An integrated active quenching circuit is of key importance for an accurate evaluation of the SPAD performances (DCR, after pulsing probability, PDP, timing jitter). This electronics will be developed in future work simultaneously with the SPAD pixel optimization [3][4].
Contacts
Tulio CHAVES de ALBUQUERQUE –
Francis CALMON –
Patrick PITTET –
Collaborations & Acknowledgments
This work has been initially launched through a collation between INL and Lab Hubert Curien (Raphaël CLERC), with the support of STMicroelectronics and CEA-LETI. The authors would like to thank: STMicroelectronics for Multi-Project-Wafer access, Auvergne Rhone Alpes region (ARC6 research program 2016 no 16 – 005689 – 01) for the PhD Grant of Tulio Chaves de Albuquerque, CMP (Grenoble) for IC prototyping service, and also IngéLySE federation for fundings. Today this research is supported by the French National Research Agency (project ANR-18-CE24-0010)
References
[1] M. M. Vignetti, F. Calmon, P. Lesieur, A. Savoy-Navarro “Simulation study on a novel 3D SPAD pixel in FDSOI technology” Elsevier Solid State Electronics, Vol. 128, pp. 163–171, February 2017
[2] T. Chaves de Albuquerque, F. Calmon, R. Clerc, P. Pittet, Y. Benthammou, D. Golanski, S. Jouan, D. Rideau, A. Cathelin “Integration of SPAD in 28nm FDSOI CMOS technology” ESSDERC 2018, 3-6 sept. 2018, Dresden, Germany.
Fig. 2: Schematic of SPAD implementation in FDSOI CMOS technology below the buried oxide (half-cell with axial symmetry)
